1. Technical Field
The present invention relates in general to data transfers in multiprocessor systems and in particular to intervention mechanisms in multiprocessor systems. Still more particularly, the present invention relates to providing a mechanism for transferring exclusive data between processors without the extra ownership directory bit required for shared intervention.
2. Description of the Related Art
Contemporary data processing systems employ multiple processors, multilevel cache hierarchies, or both to improve performance. A conventional symmetric multiprocessor (SMP) system employs several processing elements, which may include a processor and one or more levels of cache memory, connected via a common system bus which also couples the processing elements to any additional cache memories and to system memory. In such SMP systems, each processing element is capable of acting as a system bus master, initiating bus operations affecting the storage hierarchy. Cache controllers for additional caches in the storage hierarchy are also capable of acting as the system bus master, and of snooping bus operations initiated by other devices connected to the system bus. Devices may also intervene in snooped bus operations in order to maintain a coherent memory hierarchy.
Multiprocessor data processing systems frequently employ the concept of logical "ownership" of data to which all processors share access in order to preserve coherency (data integrity), a concept which forms the basis for intervention. Devices such as processors and cache controllers may intervene in snooped bus operations in order to preserve data integrity within the storage hierarchy. For example, where one device initiates a read or read with intent to modify (rwitm) request for specified data which is resident within a second device in the modified state, the second device intervenes in the bus operation for the purpose of sourcing the modified data to the requesting device (a "modified intervention"). Similarly, where data requested by a read or rwitm bus operation is resident within a device in the shared state, the device intervenes with the requested data (a "shared intervention").
Shared intervention is employed in multiprocessor systems to improve latency, since horizontal cache devices may frequently source requested data much faster than system memory. The cache coherency state transitions associated with a shared intervention are tabulated in FIG. 4. A device seeking to load a shared cache line owned by a horizontal device will receive a shared intervention from the horizontal device, which will then source the data to the requesting device. Similarly, a device seeking to store to a shared cache line owned by a horizontal device will also receive a shared intervention from the horizontal device, although no data need be sourced to the requesting device. In both cases, "ownership" of the cache line passes from the horizontal device to the requesting device.
Shared intervention allows a processor or an in-line cache to own a shared cache line, as opposed to the conventional ownership by memory of all shared cache lines. However, the owner of the shared cache line must be marked, and ownership is generally recorded in an extra tag or status bit within the cache directories. The extra bit is set when ownership of the shared cache line is received, and a device with this ownership bit set will respond to future requests for the cache line with a shared intervention. Shared intervention_allows fast cache-to-cache transfers to supplant possibly much slower accesses to memory.
It would be desirable, therefore, to provide a mechanism for unmodified intervention without the additional requirements of an extra directory tag or status bit.